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sn74cbtlv3253 scds039i ? december 1997 ? revised september 2015 sn74cbtlv3253 low-voltage dual 1-of-4 fet multiplexer/demultiplexer 1 features 3 description the sn74cbtlv3253 device is a dual 1-of-4 high- 1 ? functionally equivalent to qs3253 speed fet multiplexer and demultiplexer. the low ? 5- switch connection between two ports on-state resistance of the switch allows connections ? rail-to-rail switching on data i/o ports to be made with minimal propagation delay. ? i off supports partial-power-down mode operation the select (s0, s1) inputs control the data flow. the ? latch-up performance exceeds 100 ma per fet multiplexers/demultiplexers are disabled when jesd 78, class ii the associated output-enable ( oe) input is high. the sn74cbtlv3253 device is fully specified for 2 applications partial-power-down applications using i off . the i off feature ensures that damaging current will not ? video broadcasting: ip-based multi-format backflow through the device when it is powered transcoders down. the device has isolation during power off. ? video communications systems device information (1) part number package body size (nom) sn74cbtlv3253d soic (16) 9.90 mm 3.90 mm sn74cbtlv3253dbq ssop (16) 4.90 mm 3.90 mm sn74cbtlv3253dgv tvsop (16) 3.60 mm 4.40 mm sn74cbtlv3253rgy vqfn (16) 4.00 mm 3.50 mm sn74cbtlv3253pw tssop (16) 5.00 mm 4.40 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. logic diagram (positive logic) 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. 2b1 1b1 2a 1a s0s1 1oe 2oe 1b21b3 1b4 2b2 2b3 2b4 sw sw sw sw sw sw sw sw 79 14 2 1 15 65 4 3 10 11 1213 productfolder sample &buy technical documents tools & software support &community
sn74cbtlv3253 scds039i ? december 1997 ? revised september 2015 www.ti.com table of contents 8.3 feature description ................................................... 8 1 features .................................................................. 1 8.4 device functional modes .......................................... 8 2 applications ........................................................... 1 9 application and implementation .......................... 9 3 description ............................................................. 1 9.1 application information .............................................. 9 4 revision history ..................................................... 2 9.2 typical application ................................................... 9 5 pin configuration and functions ......................... 3 10 power supply recommendations ..................... 10 6 specifications ......................................................... 4 11 layout ................................................................... 11 6.1 absolute maximum ratings ..................................... 4 11.1 layout guidelines ................................................. 11 6.2 esd ratings .............................................................. 4 11.2 layout example .................................................... 11 6.3 recommended operating conditions ...................... 4 12 device and documentation support ................. 12 6.4 thermal information .................................................. 4 12.1 documentation support ....................................... 12 6.5 electrical characteristics .......................................... 5 12.2 community resources .......................................... 12 6.6 switching characteristics .......................................... 5 12.3 trademarks ........................................................... 12 6.7 typical characteristics .............................................. 6 12.4 electrostatic discharge caution ............................ 12 7 parameter measurement information .................. 7 12.5 glossary ................................................................ 12 8 detailed description .............................................. 8 13 mechanical, packaging, and orderable 8.1 overview ................................................................... 8 information ........................................................... 12 8.2 functional block diagram ......................................... 8 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision h (february 2014) to revision i page ? added applications section, device information table, pin configuration and functions section, esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section ..................................................................................................................... 1 changes from revision g (february 2014) to revision h page ? updated data sheet ? no specific changes ........................................................................................................................... 1 changes from revision f (july 2012) to revision g page ? deleted ordering information table. ....................................................................................................................................... 1 2 submit documentation feedback copyright ? 1997 ? 2015, texas instruments incorporated product folder links: sn74cbtlv3253
sn74cbtlv3253 www.ti.com scds039i ? december 1997 ? revised september 2015 5 pin configuration and functions d, dbq, dgv, or pw package 16-pin soic, ssop, tvsop, or tssop top view rgy package 16-pin vqfn top view pin functions pin i/o description name no. 1 oe 1 i output enable 1 active-low s1 2 i select pin 1 1b4 3 i/o channel 1 i/o 4 1b3 4 i/o channel 1 i/o 3 1b2 5 i/o channel 1 i/o 2 1b1 6 i/o channel 1 i/o 1 1a 7 i/o channel 1 common gnd 8 ? ground 2a 9 i/o channel 2 common 2b1 10 i/o channel 2 i/o 1 2b2 11 i/o channel 2 i/o 2 2b3 12 i/o channel 2 i/o 3 2b4 13 i/o channel 2 i/o 4 s0 14 i select pin 0 2 oe 15 i output enable 2 active-low v cc 16 ? power copyright ? 1997 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: sn74cbtlv3253 1 16 8 9 23 4 5 6 7 1514 13 12 11 10 2oe s02b4 2b3 2b2 2b1 s1 1b41b3 1b2 1b1 1a 1oe 2a v gnd cc 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 1oe s1 1b41b3 1b2 1b1 1a gnd v cc 2oe s02b4 2b3 2b2 2b1 2a
sn74cbtlv3253 scds039i ? december 1997 ? revised september 2015 www.ti.com 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage ? 0.5 4.6 v v in control input voltage (2) ? 0.5 4.6 v v i/o switch i/o voltage (2) ? 0.5 4.6 v i ik control input clamp current v in < 0 ? 50 ma i i/ok i/o port clamp current v i/o < 0 ? 50 ma continuous current through v cc or gnd 128 ma t j junction temperature 150 c t stg storage temperature ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 6.2 esd ratings value unit human body model (hbm), per ansi/esda/jedec js-001, all pins (1) +2000 v electrostatic v esd charged-device model (cdm), per jedec specification jesd22-c101, all discharge +1000 v pins (2) (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage 2.3 3.6 v v cc = 2.3 v to 2.7 v 1.7 v ih high-level control input voltage v v cc = 2.7 v to 3.6 v 2 v cc = 2.3 v to 2.7 v 0.7 v il low-level control input voltage v v cc = 2.7 v to 3.6 v 0.8 t a operating free-air temperature ? 40 85 c (1) all unused control inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , scba004 . 6.4 thermal information sn74cbtlv3253 d dbq dgv pw rgy thermal metric (1) unit (soic) (ssop) (tvsop) (tssop) (vqfn) 16 pins 16 pins 16 pins 16 pins 16 pins r ja junction-to-ambient thermal resistance 73 90 120 108 39 c/w (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 4 submit documentation feedback copyright ? 1997 ? 2015, texas instruments incorporated product folder links: sn74cbtlv3253
sn74cbtlv3253 www.ti.com scds039i ? december 1997 ? revised september 2015 6.5 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ (1) max unit v ik v cc = 3 v, i i = ? 18 ma ? 1.2 v i i v cc = 3.6 v, v i = v cc or gnd 1 a i off v cc = 0, v i or v o = 0 to 3.6 v 15 a i cc v cc = 3.6 v, i o = 0, v i = v cc or gnd 10 a control other inputs at v cc or ? i cc (2) v cc = 3.6 v, one input at 3 v, 300 a inputs gnd control c i v i = 3 v or 0 3 pf inputs a port 20.5 c io(off) v o = 3 v or 0, oe = v cc pf b port 5.5 i i = 64 ma 5 8 v i = 0 v cc = 2.3 v, i i = 24 ma 5 8 typ at v cc = 2.5 v v i = 1.7 v, i i = 15 ma 27 40 r on (3) ? i i = 64 ma 5 7 v i = 0 v cc = 3 v i i = 24 ma 5 7 v i = 2.4 v, i i = 15 ma 10 15 (1) all typical values are at v cc = 3.3 v (unless otherwise noted), t a = 25 c. (2) this is the increase in supply current for each input that is at the specified voltage level, rather than v cc or gnd. (3) measured by the voltage drop between the a and the b terminals at the indicated current through the switch. on-state resistance is determined by the lower of the voltages of the two (a or b) terminals. 6.6 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see figure 2 ) v cc = 2.5 v v cc = 3.3 v from to 0.2 v 0.3 v parameter unit (input) (output) min max min max a or b (1) b or a 0.15 0.25 t pd ns s a or b 1 6.8 1 5.5 t en s a or b 1 4.3 1 4 ns t dis s a or b 1 5.1 1 5.5 ns t en oe a or b 1 5 1 4.8 ns t dis oe a or b 1 5.5 1 5.4 ns (1) the propagation delay is the calculated rc time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). copyright ? 1997 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: sn74cbtlv3253
sn74cbtlv3253 scds039i ? december 1997 ? revised september 2015 www.ti.com 6.7 typical characteristics figure 1. v o vs v i , v cc = 2.5 v 6 submit documentation feedback copyright ? 1997 ? 2015, texas instruments incorporated product folder links: sn74cbtlv3253 v i 0 1 2 3 0 1 2 3 v o ?40 c 25 c 85 c
sn74cbtlv3253 www.ti.com scds039i ? december 1997 ? revised september 2015 7 parameter measurement information figure 2. test circuit and voltage waveforms copyright ? 1997 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: sn74cbtlv3253 v cc /2 t h t su from output under test c l (see note a) load circuit s1 2 v cc open gnd r l r l data input timing input v cc 0 vv cc 0 v 0 v t w input voltage waveforms setup and hold times voltage waveforms propagation delay times voltage waveforms pulse duration t plh t phl t phl t plh v oh v oh v ol v ol v cc 0 v input output waveform 1 s1 at 2 v cc (see note b) output waveform 2 s1 at gnd (see note b) v ol v oh t pzl t pzh t plz t phz v cc 0 v v ol + v ? v oh C v ? 0 v v cc voltage waveforms enable and disable times outputoutput t plh /t phl t plz /t pzl t phz /t pzh open 2 v cc gnd test s1 output control v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc v cc /2 v cc /2 2.5 v 0.2 v 3.3 v 0.3 v 500 500 v cc r l 0.15 v 0.3 v v ? c l 30 pf 50 pf
sn74cbtlv3253 scds039i ? december 1997 ? revised september 2015 www.ti.com 8 detailed description 8.1 overview the sn74cbtlv3253 device is a dual 1-of-4 high-speed fet multiplexer/demultiplexer. the low on-state resistance of the switch allows connections to be made with minimal propagation delay. the select (s0, s1) inputs control the data flow. the fet multiplexers and demultiplexers are disabled when the associated output-enable ( oe) input is high. the sn74cbtlv3253 device is fully specified for partial-power-down applications using i off . the i off feature ensures that damaging current will not backflow through the device when it is powered down. the device has isolation during power off. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 8.2 functional block diagram 8.3 feature description the sn74cbtlv3253 device is functionally equivalent to the qs3253 and has a 5- switch connection between two ports it also has rail-to-rail switching on data i/o ports as well as i off supporting partial-power-down mode operation 8.4 device functional modes table 1 lists the functional modes of the sn74cbtlv3253. table 1. function table (each multiplexer/demultiplexer) inputs function oe s1 s0 l l l a port = b1 port l l h a port = b2 port l h l a port = b3 port l h h a port = b4 port h x x disconnect 8 submit documentation feedback copyright ? 1997 ? 2015, texas instruments incorporated product folder links: sn74cbtlv3253 2b1 1b1 2a 1a s0s1 1oe 2oe 1b21b3 1b4 2b2 2b3 2b4 sw sw sw sw sw sw sw sw 79 14 2 1 15 65 4 3 10 11 1213
sn74cbtlv3253 www.ti.com scds039i ? december 1997 ? revised september 2015 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the sn74cbtlv3253 can be used to multiplex and demultiplex up to 2 channels simultaneously in a 4:1 configuration. the application shown here is a 2-bit bus being multiplexed between two devices. the oe and s pins are used to control the chip from the bus controller. this is a very generic example, and could apply to many situations. 9.2 typical application figure 3. typical application of the sn74cbtlv3253 9.2.1 design requirements the 0.1 f capacitor should be placed as close as possible to the device. 9.2.2 detailed design procedure 1. recommended input conditions: ? for specified high and low levels, see v ih and v il in recommended operating conditions . ? inputs and outputs are overvoltage tolerant slowing them to go as high as 4.6 v at any valid v cc . 2. recommended output conditions: ? load currents should not exceed 128 ma per channel. 3. frequency selection criterion: ? added trace resistance/capacitance can reduce maximum frequency capability; use layout practices as directed in layout . copyright ? 1997 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: sn74cbtlv3253 2
sn74cbtlv3253 scds039i ? december 1997 ? revised september 2015 www.ti.com typical application (continued) 9.2.3 application curve figure 4. r on vs v i , v cc = 2.5 v 10 power supply recommendations the power supply can be any voltage between the minimum and maximum supply voltage rating listed in the recommended operating conditions table. each v cc terminal should have a good bypass capacitor to prevent power disturbance. for devices with a single supply, a 0.1- f bypass capacitor is recommended. if multiple pins are labeled v cc , then a 0.01- f or 0.022- f capacitor is recommended for each v cc because the v cc pins are tied together internally. for devices with dual- supply pins operating at different voltages, for example v cc and v dd , a 0.1- f bypass capacitor is recommended for each supply pin. to reject different frequencies of noise, use multiple bypass capacitors in parallel. capacitors with values of 0.1 f and 1 f are commonly used in parallel. the bypass capacitor should be installed as close to the power terminal as possible for best results. 10 submit documentation feedback copyright ? 1997 ? 2015, texas instruments incorporated product folder links: sn74cbtlv3253 v i 0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 3 r on 85 c ?40 c 25 c
sn74cbtlv3253 www.ti.com scds039i ? december 1997 ? revised september 2015 11 layout 11.1 layout guidelines reflections and matching are closely related to the loop antenna theory but are different enough to be discussed separately from the theory. when a pcb trace turns a corner at a 90 angle, a reflection can occur. a reflection occurs primarily because of the change of width of the trace. at the apex of the turn, the trace width increases to 1.414 times the width. this increase upsets the transmission-line characteristics, especially the distributed capacitance and self ? inductance of the trace which results in the reflection. not all pcb traces can be straight and therefore some traces must turn corners. figure 5 shows progressively better techniques of rounding corners. only the last example (best) maintains constant trace width and minimizes reflections. 11.2 layout example figure 5. trace example copyright ? 1997 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: sn74cbtlv3253 worst better best 1w min. w 2w
sn74cbtlv3253 scds039i ? december 1997 ? revised september 2015 www.ti.com 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation, see the following: implications of slow or floating cmos inputs , scba004 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 12.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 12 submit documentation feedback copyright ? 1997 ? 2015, texas instruments incorporated product folder links: sn74cbtlv3253
package option addendum www.ti.com 24-apr-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples 74cbtlv3253dbqrg4 active ssop dbq 16 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 cl253 74cbtlv3253dgvre4 active tvsop dgv 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 cl253 74cbtlv3253pwre4 active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 cl253 74CBTLV3253PWRG4 active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 cl253 sn74cbtlv3253d active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 cbtlv3253 sn74cbtlv3253dbqr active ssop dbq 16 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 cl253 sn74cbtlv3253de4 active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 cbtlv3253 sn74cbtlv3253dg4 active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 cbtlv3253 sn74cbtlv3253dgvr active tvsop dgv 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 cl253 sn74cbtlv3253dr active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 cbtlv3253 sn74cbtlv3253dre4 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 cbtlv3253 sn74cbtlv3253pw active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 cl253 sn74cbtlv3253pwg4 active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 cl253 sn74cbtlv3253pwr active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 cl253 sn74cbtlv3253rgyr active vqfn rgy 16 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 cl253 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design.
package option addendum www.ti.com 24-apr-2015 addendum-page 2 preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn74cbtlv3253dgvr tvsop dgv 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 q1 sn74cbtlv3253dr soic d 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 q1 sn74cbtlv3253pwr tssop pw 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 sn74cbtlv3253rgyr vqfn rgy 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 q1 package materials information www.ti.com 7-nov-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) sn74cbtlv3253dgvr tvsop dgv 16 2000 367.0 367.0 35.0 sn74cbtlv3253dr soic d 16 2500 333.2 345.9 28.6 sn74cbtlv3253pwr tssop pw 16 2000 367.0 367.0 35.0 sn74cbtlv3253rgyr vqfn rgy 16 3000 367.0 367.0 35.0 package materials information www.ti.com 7-nov-2013 pack materials-page 2
mechanical data mpds006c february 1996 revised august 2000 post office box 655303 ? dallas, texas 75265 dgv (r-pdso-g**) plastic small-outline 24 pins shown 14 3,70 3,50 4,90 5,10 20 dim pins ** 4073251/e 08/00 1,20 max seating plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 112 24 13 4,30 4,50 0,16 nom gage plane a 7,90 7,70 38 24 16 4,90 5,10 3,70 3,50 a max a min 6,60 6,20 11,20 11,40 56 9,60 9,80 48 0,08 m 0,07 0,40 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. d. falls within jedec: 24/48 pins mo-153 14/16/20/56 pins mo-194

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